Verilog HDL: VLSI Hardware Design Comprehensive Masterclass
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A job oriented exhaustive course on logic design for hardware using the Verilog Hardware Description Language.
Unique, tested and proven structured style and approach followed.
Thoughtful blend of theory and practice for your learning.
Unlimited support with the instructor.
Understand all the intricate details in thinking and understanding hardware design.
Principles are reinforced with multiple examples.
Good coding guidelines and bad examples to avoid.
After completing the course, you can confidently write synthesizable code for complex hardware design.
Thorough discussion of every hardware component design.
Detailed explanation of the relationship between code and digital hardware units.
Freely download 100+ code examples and test benches used in the course.
Access to all the materials and the future upgrades.
Loads to quizzes and assignments to check your understanding.
Work through the lessons at your own pace.
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1
IntroductionGet the basics right to lay a strong foundation
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2
Course coverage
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3
Review of VLSI concepts
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4
Quick CMOS basics (added as per request)
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5
What is VLSI?
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6
Review of terms
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7
Minimum feature size
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8
Why Integration?
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9
Broad areas in VLSI
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10
VLSI Design Styles - Full Custom
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11
VLSI Design Styles - Semi Custom
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12
VLSI Design Styles - FPGA
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13
VLSI Design Styles - Gate Array
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14
VLSI Design Styles - Comparison
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15
Full custom vs Semi custom
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16
ASIC vs FPGA
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17
ASIC Design Flow - Part 1
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18
ASIC Design Flow - Part 2
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19
ASIC Design Flow - Design Specs
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20
ASIC Design Flow - Architecturing
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21
ASIC Design Flow - RTL coding
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22
ASIC Design Flow - Verification
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23
ASIC Design Flow - Synthesis
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24
ASIC Design Flow - Design for Testability
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25
ASIC Design Flow - Timing Analysis
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26
ASIC Design Flow - Floorplanning, Placement & Routing
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27
ASIC Design Flow - Formal Verification
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28
ASIC Design Flow - Power Estimation
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29
ASIC Design Flow - Fabrication
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30
ASIC Design Flow - Packaging
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31
Verilog Design Styles
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32
My First Dataflow Style Design
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33
My First Behavioral Style Design
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34
My First Structural Style Design
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35
1-bit Full Adder (Sturctural-1)
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36
1-bit Full Adder (Sturctural-2)
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37
1-bit Full Adder (Sturctural-3)
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38
1-bit Full Adder (Dataflow)
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39
1-bit Full Adder (Behavioral)
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40
My first Test Bench
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41
4 Valued Logic
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42
Data Types
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43
Number Representation
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44
Bit and Bus
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45
Naming Conventions
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46
Operators - Bitwise
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47
Operators - Arithmetic
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48
Operators - Logical
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49
Operators - Relational
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50
Operators - Reduction
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51
Operators - Shift
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52
Operators - Concatenation
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53
Operators - Repetition
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54
Operators - Conditional
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55
Output Resolution Table
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56
4-bit Full Adder (Structural)
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57
4-bit Full Adder (Dataflow)
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58
4-bit Full Adder (Behavioral)
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59
4-bit Full Adder Test Bench
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60
2:1 Multiplexer (Dataflow)
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61
2:1 Multiplexer (Behavioral)
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62
4:1 Multiplexer (Dataflow1)
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63
4:1 Multiplexer (Dataflow2)
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64
4:1 Multiplexer (Dataflow3)
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65
4:1 Multiplexer (Behavioral)
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66
2 X 4 Decoder (Dataflow)
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67
2 X 4 Decoder (Behavioral)
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68
3 X 8 Decoder (Dataflow)
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69
4 X 2 Encoder (Dataflow)
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70
4 X 2 Encoder (Behavioral)
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71
4 X 2 Priority Encoder (Behavioral)
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72
4 X 2 Priority Encoder (Dataflow)
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73
4-bit Comparator (Dataflow 1)
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74
4-bit Comparator (Dataflow 2)
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75
4-bit Comparator (Behavioral)
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76
8-bit Barrel Shifter (Combinational Left & Right)
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77
Designing Arithmetic & Logic Unit (ALU)
